This invention relates generally to integrated circuit packaging and printed circuit board assembly. In particular, the invention relates to a bumped area-array device such as a flip chip attached to a printed wiring board with pre-applied underfill material, and to a method of manufacturing flip-chip assemblies using pre-applied underfill on the circuit boards.
The proliferation of bumped area-array devices such as flip-chips and ball-grid arrays during the past decade makes flip-chip die mounting a preferred approach for a widening variety of flip chips and other electronic packages. Bumped area-array devices and flip-chip assemblies can be described as active components, usually integrated circuits that are directly connected facedown to printed wiring boards (PWB) and other electronic substrates by means of conductive bumps on the chip or package bond pads. They have become popular in cost-conscious, high volume production of electronic devices such as consumer watches, smart cards, radio-frequency identification cards, and cellular telephones.
As more of these components are assembled to form cost-effective electronic modules and flip-chip assemblies, the need increases for an underfill system that obviates the time-consuming sequences required by capillary flow of underfill materials in current assembly processes. After application and heat-treatment, underfill material structurally reinforces the solder bumps, mechanically adheres the flip chip to the PWB, and improves the reliability of the assembly.
Flip chips are formed with ball-shaped beads or bumps of solder affixed to their input/output (I/O) bonding pads. The integrated circuit (IC) flip chip or die may be bonded directly to a packaging substrate or motherboard, without the need for a separate wire-bonded leadframe or for separate I/O connectors such as wires or tapes. During assembly, the chip is xe2x80x9cflippedxe2x80x9d onto its active circuit surface so that the solder balls form electrical connections directly between the bumped chip and conductive traces on an electronic substrate.
Underfill materials are typically applied between the active surface of the bumped IC and the PWB after the device has been soldered to the substrate. In the liquid underfill dispense technique, the underfill is applied at one or more edges of the flip-chip bonded die and capillary action wicks the fluid under the die. During heat treatment, the underfill material wets the die site on the PWB and the entire die surface and then is cured. When cooled, the underfill material securely bonds the die to the substrate and provides stress relief for the soldered bumps.
The capillary flow technology uses underfill material of a suitable polymer in the void between the chip and the substrate. The underfill material is typically dispensed around two adjacent sides of the bumped flip chip or area-array package, with the underfill material flowing by capillary action to fill the gap between the chip or package and the substrate. Baking or heat-treating then hardens the underfill material. If underfill material is delaminated from either the substrate or the bumped device, stress concentration and premature failure of solder joints may occur. Underfilling the chip with a subsequently cured encapsulant typically reduces solder joint cracking caused by thermal expansion mismatches between the chip and the substrate. The cured encapsulant reduces the level of stresses on the solder joints, induced by differential expansion and contraction. An example of an underfill material being applied around the periphery of a flip-chip assembly and partially wicked into the interior region is described by Raiser, et al., in U.S. Pat. No. 6,365,441, xe2x80x9cPartial Underfill for Flip Chip Electronic Packagesxe2x80x9d issued Apr. 2, 2002.
Underfill methods may use an underfill layer on the active surface of the bumped chip and flux applied to a printed circuit board (PCB). Yamaji presents an underfill on the surface of a chip to the top ends of the bumps, as described in U.S. Pat. No. 5,925,936, xe2x80x9cSemiconductor Device for Face Down Bonding to a Mounting Substrate and a Method of Manufacturing the Samexe2x80x9d issued Jul. 20, 1999. Capote and others disclose a simplified process for flip-chip attachment to a substrate, which pre-coats the bumped IC chip with an encapsulant underfill material, as described in U.S. Pat. No. 6,121,689, xe2x80x9cSemiconductor Flip-Chip Package and Method for the Fabrication Thereofxe2x80x9d issued Sept. 19, 2000. The encapsulant encases the bumps that extend from contacts on the surface of the chip to the pads of the substrate.
An underfill process using intermixed flux and underfill that are applied to the die are described in U.S. Pat. No. 6,194,788, xe2x80x9cFlip Chip with Integrated Flux and Underfillxe2x80x9d by Gilleo et al. issued Feb. 27, 2001. The manufacturing process uses one step to apply a bumped flip chip with fluxing underfill on the bumped flip chip to a printed circuit board, rather than using separate fluxing and underfilling steps.
An underfill process using a selectively filled adhesive film with a fluxing agent in a portion of the film is described in U.S. Pat. No. 5,814,401, xe2x80x9cSelectively Filled Adhesive Film Containing a Fluxing Agentxe2x80x9d by Gamota, et al., issued Sept. 29, 1998.
Underfill material may be applied, for example, using no-flow underfill materials. The no-flow underfill materials may be dispensed, for example, with a needle dispensing system on the PCB or PWB prior to positioning the flip chips and subsequent to the heating of the assembly.
Current underfill processes make the assembly of encapsulated flip-chips on printed wire boards a time consuming, labor intensive and expensive process with a number of uncertainties. To join the bumped integrated circuit to the substrate, flux is generally is placed on the chip or electrical substrate and then the IC is placed on the substrate. The assembly is subjected to a solder reflowing thermal cycle, melting the bumps and soldering the chip to the substrate. The surface tension of the solder aids to self-align the chip to the substrate pads. Underfill encapsulation of the chip generally follows after reflow.
Major issues with the underfill process are the long processing times for both material dispensing and cure. The multi-step process of underfilling and curing of the encapsulant requires the material to flow through the tiny gap between the chip and the substrate. As the size of chips increase, the capillary action of the encapsulation procedure becomes even more time-consuming, and is more susceptible to void formation and to the separation of the polymer from fillers during application. Another general problem is that any flux residue remaining in the gap may reduce the adhesive and cohesive strengths of the underfill-encapsulating adhesive. Furthermore, as the pitch between adjacent bumps decreases and the density of bumps increases, uniform flow of underfill materials becomes increasingly difficult. One solution to this problem is disclosed in U.S. Pat. No. 6,294,840, xe2x80x9cDual-Thickness Solder Mask in Integrated Circuit Package,xe2x80x9d by McCormick, issued Sept. 25, 2001. This method requires two or more masks, each requiring alignment and intermediate processing.
Application of underfill materials at the wafer level, while attractive for large quantities of cost-effective bumped flip chips, requires uniformly applied underfill material around each of the bumps and well-controlled underfill thickness. Processes to achieve this on a bumped wafer are expensive and inefficient. It is difficult to gel sufficiently level coating between the bumps due to surface tension effects.
Application of the material may be to an unbumped wafer, but an added process step is required to form openings in the underfill coating. Also, the chemistry of the underfill is complicated by the need for photosensitivity. Wafer-applied underfill techniques are generally not directly applicable to other types of bumped devices such as bumped area-array packages.
Once coated, assembly of the flip chips to the PCB or PWB is complicated by the presence of the underfill. It is difficult for an automated component placement machine to recognize the bumps used for alignment because of the surrounding underfill, which interferes with vision recognition. Also, the coated chip must be held in place after placement and prior to soldering, requiring special equipment or processing steps. For example, the surface of the underfill may be heated prior to placement to soften the underfill and create a tacky surface for bonding to the PCB.
It would be beneficial to have a packaging technology for directly attaching area-array devices such as bumped flip chips to an underlying electrical substrate such as a PWB that allows secure electrical and mechanical die attach to the PWB, while eliminating the need for time-consuming dispensing operations for dispensing underfill materials around attached flip chips, as required by current capillary flow underfill methods. The packaging technology would allow bumped devices to be bonded effectively to an electrical substrate, with highly reliable electrical interconnections and protective underfill material for secure die bonding, stress relief for the bumps, and effective environmental protection. Furthermore, the technology would not require pre-coating material to the solder bumps, would eliminate bump-recognition challenges, would eliminate an additional tacking step typically needed to maintain alignment during reflow.
It is an object of this invention, therefore, to provide an improved method for attaching bumped area-array devices to an electrical substrate and a process for effectively and inexpensively applying underfill, having improvements that overcome the deficiencies and obstacles described above.
One aspect of the invention provides a method of attaching a bumped area-array device such as a bumped flip chip to an electrical substrate. An underfill material is applied to a portion of the electrical substrate. The applied underfill material is heated to an underfill-material staging temperature. A bumped area-array device is provided, the bumped area-array device including an interconnection surface and a plurality of connective bumps extending from the interconnection surface. The interconnection surface of the bumped area-array device is positioned adjacent the applied underfill material. The bumped area-array device is heated to electrically connect the connective bumps to the electrical substrate, and the underfill material flows around the bumps.
Another aspect of the invention provides a bumped area-array device assembly. The bumped area-array assembly includes a bumped flip chip with an active surface and a plurality of connective bumps extending from the active surface, and an electrical substrate with a pre-applied underfill material at a flip-chip receiving region. The flip chip is heated to electrically connect the connective bumps to the electrical substrate and to flow the underfill material from the flip-chip receiving region around the connective bumps to secure the flip chip to the electrical substrate
Another aspect of the invention provides a printed wiring board panel with pre-applied underfill material, having a single-layer or a multiple-layer printed circuit board that includes a pre-applied underfill material disposed on a surface of the printed circuit board at a plurality of flip-chip receiving regions. The flip-chip receiving regions indicate flip-chip placement during flip-chip assembly.
The present invention is illustrated by the accompanying drawings of various embodiments and the detailed description given below. The drawings should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof. The foregoing aspects and other attendant advantages of the present invention will become more readily appreciated by the detailed description taken in conjunction with the accompanying drawings.